The I/O interface of a typical integrated circuit (IC), such as a field programmable gate array (FPGA), may support or be configured to support a variety of I/O standards including such single-ended I/O standards as: low-voltage complementary metal oxide semiconductor (LVCMOS); low-voltage transistor-transistor logic (LVTTL); high-speed transceiver logic (HSTL); stub-series terminated logic (SSTL); gunning transceiver logic (GTL); and peripheral component interface (PCI). Differential I/O standards may also be supported by a typical FPGA, such as: low-voltage differential signaling (LVDS); LVDS extended; low-voltage, positive emitter coupled logic (LVPECL); bus LVDS (BLVDS); differential HSTL; stub-series terminated logic (SSTL); and hypertransport protocol (HT).
Furthermore, a typical application may implement many of the I/O standards listed above in a simultaneous fashion. For instance, an FPGA application may employ several I/O interfaces to support several I/O standards all at the same time. For example, one or more I/O banks of the FPGA may be used to implement a double data rate two (DDR2) synchronous dynamic random access memory (SDRAM) interface for high-speed data access using an SSTL I/O standard. One or more I/O banks of the FPGA may also be used to implement a flat-panel display driver interface using an LVDS I/O standard. In addition, one or more I/O banks of the FPGA may be used to implement a relatively low frequency control interface using an LVCMOS I/O standard.
As such, a high probability exists that simultaneously transitioning logic states of one or more output drivers of the FPGA will create power supply disturbances, which will affect the performance of other output drivers operating within the FPGA. Simultaneous switching events may also contribute to electromagnetic (EM) coupling disturbances, in which transient energy from a so-called “aggressor” signal path is electromagnetically coupled onto a so-called “victim” signal path. Both the power supply disturbances and the EM coupling disturbances combine to form simultaneous switching output (SSO) noise, which may result in undesirable behavior in the output drivers, input receivers, and internal logic of an IC.
Prediction of the time varying characteristics of SSO noise in any particular application is important, since SSO noise is a major factor leading to signal integrity corruption within silicon device packages, printed circuit boards (PCBs), signal transmission media, etc. Furthermore, the effects of SSO noise are exacerbated by noise margins that are continuously being decreased through reductions in the signal amplitude, as defined by the I/O standards.
Prediction of SSO noise, however, is extremely difficult in conventional FPGAs, as well as other integrated circuits, due to a number of factors. First, a large number of nodes are generally contributing to each SSO noise event, where each node makes its own unique contribution to each SSO noise event. In addition, the EM coupling characteristics of each node are non-uniform and complex due in large part to the 3-dimensional structures of conventional integrated circuits and device packages.
Conventional methods used to characterize SSO noise events have employed 3-dimensional modeling tools, such as HFSS™ from Ansoft Corp. Such 3-dimensional modeling tools, however, require high-performance computing platforms due to the computationally intensive algorithms that are executed by the 3-dimensional modeling tools. Even with the use of high-performance computing platforms, practical simulation runs must be limited to a relatively small number of electrical nodes due to the computational resources that are required.
Other SSO noise prediction methods attempt to approximate the electrical characteristics of the structures being simulated, so as to reduce the complexity of the computations required. Such methods, however, have received only limited success due to the lack of accuracy provided by the approximations. In particular, either the approximations completely disregard the actual electrical principles that contribute to the SSO noise events, or the electrical principles are not accurately represented when they are approximated.
Efforts continue, therefore, to simplify SSO noise prediction algorithms so as to reduce the complexity of the computing architectures that are required to execute the SSO noise prediction algorithms. Furthermore, efforts continue to improve the accuracy of the SSO noise prediction algorithms so as to increase the confidence level achieved when utilizing them.